The present invention relates to a semiconductor design technology; and more particularly, to an internal voltage generation circuit for generating an internal voltage.
In general, an internal voltage generation circuit is mounted on a semiconductor device, i.e., a Double Date Rate Synchronous DRAM (DDR SDRAM). The semiconductor consumes power efficiently and executes a more stable circuit operation by using an internal voltage of various voltage levels. A peripheral voltage and a core voltage as an internal voltage are generated by down-converting an external power voltage. A pumping voltage and a substrate bias voltage as an internal voltage are generated by pumping the external power voltage and a ground power voltage.
Meanwhile, as a semiconductor device is integrated highly, a design-rule below a sub-micron level is applied to design of an internal circuit, and an operation frequency of the semiconductor device is getting higher. An external power voltage must be basically lowered for the microcircuits to perform a high frequency operation. Thus, nowadays, researchers endeavor to generate stable internal voltage using a lowered external power voltage. Especially, because a pumping voltage, which is generated by pumping the external power voltage, can be largely varied in response to a micro variation of the external power voltage, it is noted to design the pumping voltage generation circuit for generating a pumping voltage.
Moreover, the pumping voltage is used in various circuits, e.g., a memory cell, of a semiconductor device. The memory cell for storing data is configured to have one cell transistor and one cell capacitor. The pumping voltage is applied to a gate terminal of the cell transistor. Because the cell transistor performs a function of a transmission path between a bit line and the cell capacitor, if the pumping voltage is unstable, the data stored in the cell capacitor from the bit line, or the data outputted from the cell capacitor to the bit line cannot be transmitted stably. That is, the pumping voltage is an important element to store or output the data stably.
FIG. 1 is a block diagram illuminating a conventional pumping voltage generation circuit.
Referring to FIG. 1, a pumping voltage generation circuit includes a comparison unit 110, an oscillation unit 130 and a pumping unit 150. If a pumping voltage VPP that is finally generated is lower than a target voltage level, the pumping voltage generation circuit raises the pumping voltage to the target voltage level by performing a pumping operation. If the pumping voltage is higher than the target voltage level, the pumping voltage generation unit does not perform the pumping operation.
The comparison unit 110 compares a reference voltage VREF with the pumping voltage VPP that is fed back, and generates an enable signal EN_OSC for enabling the oscillation unit. The reference voltage VREF has a voltage level corresponding to the target voltage level. The enable signal EN_OSC has a logical level value of logic ‘high’ or ‘low’ based on the comparison result of the reference voltage VREF and the pumping voltage VPP.
The oscillation unit 130 generates an oscillation signal OSC having a predetermined period in response to the enable signal EN_OSC. When it is assumed that if the pumping voltage VPP is lower than the reference voltage VREF, the comparison unit 110 outputs an enable signal EN_OSC of a logic ‘high’, and if the pumping voltage VPP is higher than the reference voltage VREF, the comparison unit 110 outputs an enable signal EN_OSC of a logic ‘low’, the oscillation unit 130 generates an oscillation signal OSC having a predetermined period in response to the enable signal EN_OSC of the logic ‘high’ and generates an oscillation signal OSC which is not oscillated in response to the enable signal EN_OSC of a logical ‘low’.
The pumping unit 150 generates the pumping voltage VPP corresponding to the oscillation signal OSC. Thus, if the pumping voltage is lower than the target voltage level, the pumping unit 150 generates the pumping voltage VPP by performing the pumping operation according to the predetermined period of the oscillation signal OSC. If the pumping voltage VPP is raised to the target voltage level through the pumping operation, the pumping unit 150 is disabled and the pumping operation of the pumping unit 150 stops. The pumping voltage generation circuit generates the pumping voltage VPP corresponding to the target voltage level and higher than an external power voltage through the operation of the components in the pumping voltage generation circuit.
Moreover, the pumping voltage VPP must be maintained to the target voltage level, but the voltage level of the pumping voltage is lower than the target voltage level in an operation which consumes a lot of the pumping voltage. The lowered pumping voltage VPP performs the pumping operation in response to the oscillation signal OSC, which has a predetermined period and is fed back to the target voltage level. That is, the pumping operation is performed in response to the predetermined period of the oscillation signal.
Here, the period of the oscillation signal OSC is determined based on various components such as a circuit operation or power consumption. This is because if the period of the oscillation signal OSC is designed to be short, unnecessary power consumption can occur, and if the period of the oscillation signal OSC is designed to be too long, it is difficult to feed back the pumping voltage to the target voltage level. Thus, a designer determines the oscillation signal OSC based on all conditions and designs the oscillation unit 130 in response to the period of the oscillation signal.
However, it is difficult to optimize the oscillation signal having the predetermined period to satisfy the circuit operation and the power consumption. That is, if the period of the oscillation signal OSC is small to increase the pumping operation speed, the unnecessary power consumption occurs, and if the period of the oscillation signal OSC is large to reduce the power consumption, the pumping operation slows down.